rvsail / boom

BOOM v3 in your browser

An unmodified SonicBOOM (BOOM v3) superscalar out-of-order RISC-V core, synthesised to a flat Verilog netlist, verilated to C++, compiled to WebAssembly, and stepped cycle by cycle right here. Not an ISA emulator — this is the RTL.
idle
0
cycles
0
instructions retired
0.00
IPC
0
AXI4 reads
0
AXI4 writes
sim kHz

Retired instruction stream trace_traces_0_trace_insns_0

AXI4 memory traffic address × cycle

read burst write burst

Program under test RV64IM, 108 bytes @ 0x80000000

# 1. pure compute: sum 1..100 = 5050
    li   t0, 0
    li   t1, 100
1:  add  t0, t0, t1
    addi t1, t1, -1
    bnez t1, 1b

# 2. read probe: 32 loads, 4 KiB apart
    li   t2, 0x80100000
    li   t3, 32
2:  ld   t4, 0(t2)
    add  t0, t0, t4
    li   t5, 4096
    add  t2, t2, t5
    addi t3, t3, -1
    bnez t3, 2b

# 3. write probe: 256 stores, 4 KiB apart
    li   t2, 0x80200000
    li   t3, 256
3:  sd   t0, 0(t2)
    li   t5, 4096
    add  t2, t2, t5
    addi t3, t3, -1
    bnez t3, 3b

# 4. read it back -> 5050 appears in the trace
    li   t2, 0x80200000
    ld   t6, 0(t2)
4:  j    4b
What you are looking at. The first ~30 retired instructions come from the on-chip BootROM at 0x10000: it parks hart 0 in wfi, the custom_boot pin drives an on-chip TileLink master that writes the boot-address register and sends a software interrupt, and the trap handler mrets to 0x80000000. From there the stream is the program on the right.

Watch the read probe in the plot: the program issues its loads at strictly increasing 4 KiB strides, but they arrive on the memory bus out of order — that is BOOM's out-of-order engine and its concurrent miss handling, visible from outside the chip.

Memory is an AXI4 behavioural model written in C++ and compiled into the same wasm module; there is no fesvr, no TSI, and no server. Everything runs in a Web Worker on your machine.